1. Field of the Invention
The present invention relates to a method and process for design of integrated circuits using regular geometry patterns to obtain component features that are geometrically consistent and, more particularly to the design of integrated circuits that have memory cells and logic components using regular geometry patterns to obtain geometrically consistent component features.
2. Background of the Invention
The active devices (transistors) and metal interconnecting layers for an integrated circuit (IC) are typically created by printing geometrical shapes onto a mask, then using a lithography process to translate said shapes onto layers of materials that define the shapes for the corresponding fabrication steps. Upon completion of multiple stages of said steps, including the layering of materials, three dimensional devices and interconnecting layers are ultimately produced to form the integrated circuit. As feature sizes are scaled well below the wavelengths of the light that are used for this lithography, the shapes of the mask geometries must be drawn substantially different from the shapes that are to be defined on the fabrication materials due to the need for resolution enhancement techniques (RETs) and optical proximity correction (OPC).
In further detail, as illustrated in FIG. 1, the traditional design flow for an Application-Specific Integrated Circuit (ASIC) that contains both memory cells/blocks and logic gates/blocks is illustrated. The memory bit-cells are carefully designed in silicon one or more times for a specific technology, then compiled into a memory block using software that is referred to as a memory compiler. The printability of the memory cells are controlled for compilation of memory blocks of any size by the design and silicon testing of bit-cells that are surrounded by identical neighboring bit-cells. To ensure proper control of the lithography process, the number of neighborhood cells required for a test-run of silicon is based on the silicon technology, the illumination controls and equipment used for lithography, and the manufacturing processes.
In contrast to the memory block design, referring to the left side of FIG. 1, the traditional design flow for the logic portion of an IC, particularly an ASIC, corresponds to: designing a library of cells in test runs of silicon; characterizing the cells in terms of their layouts and performances; configuring interconnections of cells as part of technology mapping step for logic synthesis; and arranging as part of the physical design step to create a logic block.
In this traditional flow, the lithography is controlled by post-processing of the geometrical patterns that are generated for physical design during the step that we refer to as the manufacturing interface in FIG. 1. It is important to note that the logic gates are designed without regular geometry pattern constraints, and their boundaries with neighboring cells in the final layout are not constrained for printability, and as such the manufacturing interface may not be able to ensure a high yield in terms of properly functioning (both logical operation correctness and performance) integrated circuits.
Test structures are presently used to evaluate the printability of fundamental components, circuit primitives, and/or design rules, however these existing methodologies do not otherwise restrict the allowable geometry patterns from which the IC is constructed.
What is needed is a means of fabricating silicon test structures to define uniform patterns of geometrical shapes that establish the underlying physical regularity from which the electronic devices and associated interconnects may be constructed.